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19-2673; Rev 0; 10/02
2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
General Description
The MAX6853 compact vacuum-fluorescent display (VFD) controller provides microprocessors with the multiplex timing for 5 x 7 matrix VFD displays up to 96 characters and controls industry-standard, shift-register, high-voltage grid/anode VFD tube drivers. The device supports display tubes using either one or two digits per grid, as well as universal displays. The MAX6853 provides an internal crosspoint switch to match any tube-driver shift-register grid/anode order, and is compatible with both chip-in-glass and external tube drivers. Hardware is included to simplify the generation of cathode bias and filament supplies and to provide up to five logic outputs, including a buzzer driver. The MAX6853 includes an ASCII 104-character font, multiplex scan circuitry, and static RAM that stores digit, cursor, and annunciator data, as well as font data for 24 user-definable characters. An internal 16-step digital brightness control adjusts the display intensity. The device also includes separate annunciator and cursor control with automatic blinking, as well as a lowpower shutdown mode. The MAX6853 provides timing to generate the PWM waveforms to drive the tube filament from a DC supply. The filament drive is synchronized to the display multiplexing to eliminate beat artifacts. For an SPITM-compatible version, refer to the MAX6852 data sheet. o 2.7V to 3.6V Operation o Controls Up to 96 5 x 7 Matrix Characters o One Digit and Two Digits per Grid and Universal Displays Supported o 16-Step Digital Brightness Control o Built-In ASCII 104-Character Font o 24 User-Definable Characters o Up to Four Annunciators per Grid with Automatic Blinking Control o Separate Cursor Control with Automatic Blinking o Filament Drive Full-Bridge Waveform Synthesis o Buzzer Tone Generator with Single-Ended or Push-Pull Driver o Up to Five General-Purpose Logic Outputs o 9A Low-Power Shutdown (Data Retained) o 16-Pin QSOP Package
Features
o 400kbps 2-Wire I2C-Compatible Interface
MAX6853
Ordering Information
PART MAX6853AEE TEMP RANGE -40C to +125C PIN-PACKAGE 16 QSOP
Applications
Display Modules Retail POS Displays Weight and Tare Displays Bar Graph Displays Industrial Controllers
Typical Application Circuit
CHIP-ON-GLASS VFD VFD SUPPLY VOLTAGE 0.1F V+
MICROCONTROLLER
VFCLK VFDOUT VFLOAD
SDA SCL
SDA SCL
MAX6853
Pin Configuration and Functional Diagram appear at end of data sheet. SPI is a trademark of Motorola, Inc.
VFBLANK AD0 OSC2 OSC1 10k 56pF
GND
________________________________________________________________ Maxim Integrated Products
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND) V+ .............................................................................-0.3V to +4V AD0, SDA, SCL......................................................-0.3V to +5.5V All Other Pins................................................-0.3V to (V+ + 0.3V) Current V+..................................................................................200mA GND .............................................................................-200mA PHASE1, PHASE2, PORT0, PORT1, PUMP................150mA VFCLK, VFDOUT, VFLOAD, VFBLANK ......................150mA SDA .................................................................................15mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate at 8.34mW/C above +70C).....667mW Operating Temperature Range (TMIN, TMAX) MAX6853AEE................................................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Operating Supply Voltage Shutdown Supply Current SYMBOL V+ ISHDN Shutdown mode, all digital inputs at V+ or GND OSC = 4MHz VFLOAD, VFDOUT, VFCLK, VFBLANK, loaded 100pF TA = TMIN to TMAX TA = +25C Operating Supply Current I+ TA = TMIN to TMAX TA = +25C 1.65 4 9 CONDITIONS MIN 2.7 TYP MAX 3.6 160 20 3 2 MHz mA UNITS V A
Master Clock Frequency (OSC Internal Oscillator) Master Clock Frequency (OSC External Oscillator) Dead-Clock Protection Frequency OSC High Time OSC Low Time Fast or Slow Segment Blink Duty Cycle LOGIC INPUTS AND OUTPUTS Input Leakage Current AD0, SDA, SCL Logic-High Input Voltage AD0, SDA, SCL Logic-Low Input Voltage AD0, SDA, SCL SDA Output Low Voltage Input Capacitance
fOSC
OSC1 fitted with COSC = 56pF, OSC2 fitted with ROSC = 10k; see the Typical Operating Circuit OSC1 overdriven with external fOSC 2
8 200
MHz kHz ns ns
tCH tCL (Note 2)
50 50 49.5 50.5
%
IIH, IIL VIH VIL VOLSDA CI ISINK = 3mA 2.4
0.2
1
A V
0.6 0.5 10
V V pF
2
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Output Rise and Fall Time PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Output High-Voltage PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Output Low-Voltage PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Output Short-Circuit Source Current PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Output Short-Circuit Sink Current PHASE1, PHASE2, PORT0, PORT1, PUMP, VFLOAD, VFDOUT, VFCLK, VFBLANK Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6853
tRFT
CLOAD = 100pF
25
ns
VOH
ISOURCE = 10mA
V+ - 0.6
V
VOL
ISINK = 10mA
0.4V
V
IOHSC
Output programmed high, output short circuit to GND (Note 2)
62
125
mA
IOLSC
Output programmed low, output short circuit to V+ (Note 2)
72
125
mA
I2C TIMING CHARACTERISTICS (Figure 6) fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tR tF (Notes 2, 4) (Notes 2, 4) (Note 3) 100 1.3 0.6 20 + 0.1CB 20 + 0.1CB 300 300 1.3 0.6 0.6 0.6 0.9 400 kHz s s s s s ns s s ns ns
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Fall Time of SDA Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line VFCLK Clock Period VFCLK Pulse Width High VFCLK Pulse Width Low VFCLK Rise to VFD Load Rise Hold Time VFDOUT Setup Time VFLOAD Pulse High SYMBOL tF tSP CB (Notes 2, 5) (Note 6) (Note 2) 0 CONDITIONS MIN TYP 20 + 0.1CB 50 400 MAX 250 UNITS ns ns pF
VFD INTERFACE TIMING CHARACTERISTICS (Figure 14) tVCP tVCH tVCL tVCSH tVDS tVCSW (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 250 125 125 19 50 245 1050 ns ns ns s ns ns
Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 4: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+. Note 5: ISINK 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+. Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(Typical Operating Circuit, V+ = 3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX6853 toc01
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (OSC = 1)
45 40 35
ISUPPLY (A)
SHUTDOWN SUPPLY CURRENT vs. EXTERNAL OSC FREQUENCY
MAX6853 toc02
MAX6853 toc03
2.1
50 OSC1 = 0 TA = +125C
1400 1200 1000
ISUPPLY (A)
1.9
TA = +125C
ICC (mA)
1.7 TA = +25C 1.5
30 25 20 15 TA = +25C TA = -40C 2.7 2.9 3.1 V+ (V) 3.3 3.5
800 600 400 200 0 2 3 4 5 6 7 8 FREQUENCY (MHz)
1.3
TA = -40C
10 5
1.1 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V)
0
4
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V+ = 3.3V, TA = +25C, unless otherwise noted.)
OUTPUT LOW VOLTAGE vs. ISINK
MAX6853 toc04
MAX6853
OUTPUT LOW VOLTAGE vs. ISINK
MAX6853 toc05
OUTPUT LOW VOLTAGE vs. ISINK
1.8 1.6 1.4
VOL (V)
MAX6853 toc06
2.0 1.8 1.6 1.4
VOL (V)
2.0 1.8 1.6 1.4
VOL (V)
2.0 V+ = 2.7V V+ = 3.3V
V+ = 2.7V V+ = 3.3V
V+ = 2.7V V+ = 3.3V
1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 ISINK (mA) 80 100 V+ = 3.6V TA = -40C
1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 ISINK (mA) 80 100 TA = +25C V+ = 3.6V
1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100
ISINK (mA)
V+ = 3.6V
TA = +125C
VIN - VOH vs. ISOURCE
MAX6853 toc07
VIN - VOH vs. ISOURCE
1.8 1.6 1.4
VOL (V)
MAX6853 toc08
VIN - VOH vs. ISOURCE
MAX6853 toc09
2.0 V+ = 2.7V 1.5
VOL (V)
2.0 V+ = 2.7V V+ = 3.3V
2.0 V+ = 2.7V 1.5
VOL (V)
V+ = 3.3V
V+ = 3.3V
1.2 1.0 0.8 0.6 0.4 0.2 TA = +25C V+ = 3.6V
1.0 V+ = 3.6V 0.5 TA = -40C
1.0 V+ = 3.6V 0.5 TA = +125C
0 0 20 60 ISOURCE (mA) 40 80 100
0 0 20 60 ISOURCE (mA) 40 80 100
0 0 20 40 60 80 100
ISOURCE (mA)
fOSC vs. TEMPERATURE
MAX6853 toc10
DEAD-CLOCK OSC FREQUENCY vs. TEMPERATURE
0.16 0.14 FREQUENCY (MHz) 0.12 0.10 0.08 0.06 V+ = 2.7V 0.04 0.02 V+ = 3.3V V+ = 3.6V
MAX6853 toc11
2.5 V+ = 2.7V 2.0 V+ = 3.3V
0.18
fOSC (MHz)
1.5
V+ = 3.6V
1.0
0.5
0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME VFCLK VFDOUT VFLOAD VFBLANK PUMP PHASE1 PHASE2 V+ GND PORT0 SCL SDA AD0 PORT1 OSC2 OSC1 FUNCTION Serial-Clock Output to External Driver. Push-pull clock output to external display driver. On VFCLK's falling edge, data is clocked out of VFDOUT. Serial-Data Output to External Driver. Push-pull data output to external display driver. Serial-Load Output to External Driver. Push-pull load output to external display driver. Rising edge is used by external display driver to load serial data into display latch. Display Blanking Output to External Driver. Push-pull blanking output to external display driver used for PWM intensity control. PUMP General-Purpose Output. User-configurable push-pull logic output. Filament Drive PHASE1 Output and General-Purpose Output. User-configurable push-pull logic output can also be used as a driver for external filament bridge drive. Filament Drive PHASE2 Output and General-Purpose Output. User-configurable push-pull logic output can also be used as a driver for external filament bridge drive. Positive Supply Voltage. Bypass V+ to GND with a 0.1F ceramic capacitor. Ground PORT0 General-Purpose Output. User-configurable push-pull logic output. Serial-Clock Input Serial-Data I/O Address Input 0. Sets device slave address. Connect to either GND, V+, SCL, or SDA to give four logic combinations. See Table 7. PORT1 General-Purpose Output. User-configurable push-pull logic output. Multiplex Clock Input 2. Connect resistor ROSC from OSC2 to GND. Multiplex Clock Input 1. To use the internal oscillator, connect capacitor COSC from OSC1 to GND. To use the external clock, drive OSC1 with a 2MHz to 8MHz CMOS clock.
GRID 1
GRID 2
GRID 3
GRID 4
GRID 5
GRID 6
GRID 7
GRID 8
GRID 9
GRID 10
GRID 11
GRID 12
GRID 13
GRID 14
GRID 15
GRID 16
Figure 1. Example of a One-Digit-per-Grid Display 6 _______________________________________________________________________________________
2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
GRID 1 GRID 2 GRID 3 GRID 4 GRID 5 GRID 6 GRID 7 GRID 8
Figure 2. Example of a Two-Digits-per-Grid Display (8 Grids, 16 Digits)
C F pH mW
4 ANNUNCIATOR SEGMENTS
Each digit can have a 5 x 7 matrix character, a DP segment, a cursor segment, and (for one-digit-per-grid displays only) four annunciators (Figure 3). The 5 x 7 matrix character segments are not controlled directly, but use on-chip fonts that map the segments. The fonts comprise an ASCII 104-character fixed-font set, and 24 user-definable characters. The predefined characters follow the Arial font, with the addition of the following common symbols: , , , , , , , and . The 24 user-definable characters are uploaded by the user into on-chip RAM through the serial interface and are lost when the device is powered down. As well as custom 5 x 7 characters, the user-definable fonts can control up to 35 custom segments, bar graphs, or graphics. Annunciator segments have individual, independent control, so any combination of annunciators can be lit. Annunciators can be off, lit, or blink either in phase or out of phase with the cursor. The blink-speed control is software selectable to be one or two blinks per second (OSC = 4MHz). DP segments can be lit or off, but have no blink control. A DP segment is set by the same command that writes the digit's 5 x 7 matrix character. The cursor segment is controlled differently. A single register selects one digit's cursor from the entire display, and that can be lit either continuously or blinking. All the other digits' cursors are off. The designations of DP, cursor, and annunciator are interchangeable. For example, consider an application requiring only one DP lit at a time, but the DP needs to
5 x 7 MATRIX CHARACTER WITH 35 SEGMENTS DECIMAL POINT (DP) SEGMENT CURSOR SEGMENT
Figure 3. Digit Structure with 5 7 Matrix Character, DP Segment, Cursor Segment, Four Annunciators
Detailed Description
Overview of the MAX6853
The MAX6853 VFD controller generates the multiplex timing for the following VFD display types: * Multiplexed displays with one digit per grid, and up to 48 grids (in 48/1 mode). Each grid can contain one 5 x 7 matrix character, a DP segment, a cursor segment, and four extra annunciator segments (Figure 1). * Multiplexed displays with two digits per grid, and up to 48 grids (in 96/2 mode). Each grid can contain two 5 x 7 matrix characters, two DP segments, and two cursor segments. No annunciator segments are supported (Figure 2).
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
3.3V MICROCONTROLLER V+
VFCLK VFDOUT VFLOAD
VFD TUBE DRIVER
SDA SCL
SDA SCL
MAX6853
GRID/ANODE DRIVERS
VFBLANK AD0 PORT0 GND PORT1 PIEZO SOUNDER 5V ZENER DIODE BIAS 115V
VFD TUBE AC FILAMENT SUPPLY FROM MAINS TRANSFORMER
Figure 4. Connection of the MAX6853 to VFD Driver and VFD Tube
VFD TUBE DRIVER VFCLK
VFDIN
SERIAL-TO-PARALLEL SHIFT REGISTER
VFLOAD
LATCHES
face uses three outputs to transfer and latch grid and anode data into the tube drivers, and a fourth output that enables/disables the tube driver outputs (Figure 5). The enable/disable control is modulated by the MAX6853 for both PWM intensity control and interdigit blanking, and disables the tube driver in shutdown. The controller multiplexes the display by enabling each grid of the VFD in turn for 100s (OSC = 4MHz) with the correct segment (anode) data. The data for the next grid is transferred to the tube drivers during the display time of the current grid. The controller uses an internal output map to match any tube-driver's shift-register grid/anode order, and is therefore compatible with all VFD internal chip-in-glass or external tube drivers. The MAX6853 provides five high-current output ports, which can be configured for a variety of functions: The PUMP output can be configured as either an 80kHz (OSC = 4MHz) clock intended for DC-to-DC converter use or a general-purpose logic output. The PHASE1 and PHASE2 outputs can be individually configured as either 10kHz PWM outputs (OSC = 4MHz) intended for filament driving, blink status outputs, or general-purpose logic outputs. The PORT0 and PORT1 outputs can be individually configured as either 625Hz, 1250Hz, or 2500Hz clocks (OSC = 4MHz) intended for buzzer driving, blink or shutdown status outputs, or general-purpose logic outputs.
VFBLANK
O0 O0
O1 O1
O2 O2
On-2 On-2
On-1 On-1
On On
VFD TUBE SIMPLIFIED
Figure 5. Block Diagram of VFD Tube Driver and VFD Tube
blink. The DP function does not have blink capability. Instead, the DP segments on the display are routed (using the output map) to the cursor function. In this case, the DP segments are controlled using the cursor register. The output of the controller is a 4-wire serial stream that interfaces to industry-standard, shift-register, high-voltage grid/anode VFD tube drivers (Figure 4). This inter-
Display Modes
The MAX6853 has two display modes (Table 1), selected by the M bit in the configuration register (Table 23). The display modes trade the maximum allowable num-
8
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 1. Display Modes
DISPLAY MODE 48/1 mode MAXIMUM NO. OF DIGITS MAXIMUM NO. OF ANNUNCIATORS 4 per digit 48 grids None 2 digits per grid MAXIMUM NO. OF GRIDS DIGITS COVERED BY EACH GRID 1 digit per grid
48 digits, each with a DP segment and a cursor segment 96 digits, each with a DP segment and a cursor 96/2 mode segment
Table 2. Register Address Map
REGISTER No-op VFBLANK polarity Intensity Grids Configuration User-defined fonts Output map Display test and device ID PUMP register Filament duty cycle PHASE1 PHASE2 PORT0 PORT1 Shift limit Cursor Factory reserved. Do not write to register. COMMAND ADDRESS D15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
ber of digits (96/2 mode) against the availability of annunciator segments (48/1 mode). Table 2 is the register address map.
Initial Power-Up
Initial power-up resets all control registers, clears display segment and annunciator data, sets intensity to minimum, and enables shutdown. (Table 3).
Character Registers
The MAX6853 uses 48 character registers (48/1 mode) (Table 4) or 96 character registers (96/2 mode) (Table 5) to store the 5 x 7 characters (Table 6). Each digit is represented by 1 byte of memory. The data in the character registers does not control the character segments directly. Instead, the register data is used to address a character generator, which stores the data of the 128character font (Table 9). The lower 7 bits of the character data (D6 to D0) select a character from the font
table. The most significant bit (MSB) of the register data (D7) controls the DP segment of the digit; it is set to light the DP, cleared to leave it unlit. The character registers address maps are shown in Table 4 (48/1 mode) and Table 5 (96/2 mode). In 48/1 mode, the character registers use a single address range 0x20 to {0x20 + g}, where g is the value in the grids register (Table 25). The 48/1 mode upper address limit, when g is 0x2F, is therefore 0x4F. The address range 0x50 to 0x7F is used for annunciator data in 48/1 mode. In 96/2 mode, the character registers use two address ranges. The first row's address range is 0x20 to {0x20 + g}. The second row's address range is 0x50 to {0x50 + g}. Therefore, in 96/2 mode, the character registers are only one contiguous memory range when a 48grid display is used.
9
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Character Generator Font Mapping
The font is a 5 x 7 matrix comprising 104 characters in ROM, and 24 user-definable characters. The selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. The MSB, shown as x in the ROM map (Table 9), controls the DP segment of the digit; it is set to light the DP, cleared to leave it unlit. The character map follows the Arial font for 96 characters in the x0100000 through x1111111 range. The first 32 characters map the 24 user-definable positions (RAM00 to RAM23), plus eight extra common characters in ROM.
User-Defined Fonts
The 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in the MAX6853's internal RAM. The 120 user-definable font data entries are written and read through a single register, address 0x05. An autoincrementing font address pointer in the MAX6853 indirectly accesses the font data. The font address pointer can be written, setting one of 120 addresses between 0x00 and 0xF7, but cannot be read back. The font data is written to and read from the MAX6853 indirectly, using this font address pointer. Unused font locations can be used as general-purpose scratch RAM, noting that the font registers are only 7 bits wide, not 8.
Table 3. Initial Power-Up Register Status
REGISTER VFBLANK polarity Intensity Grids Configuration User-defined font address pointer User-defined fonts Output map pointer Output map data Display test PUMP Filament duty cycle PHASE1 PHASE2 PORT0 PORT1 Shift limit Cursor Character and annunciator data UP TO Character and annunciator data Clear POWER-UP CONDITION VFBLANK is high to disable the display 1/16 (min on) Display has 1 grid Shutdown enabled, configuration unlocked Address 0x80; pointing to the first user-defined font location All 24 characters blank Pointing to first entry address Predefined for 40-digit display Normal operation General-purpose output, logic Minimum duty cycle General-purpose output, logic General-purpose output, logic General-purpose output, logic General-purpose output, logic 2 output bits Off Clear -- COMMAND ADDRESS 0x01 0x02 0x03 0x04 0x05 -- 0x06 -- 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x20 UP TO 0x7F 0 0 0 0 0 0 0 X 0 0 -- 0 0 0 0 0 0 0 0 0 1 0 -- 0 REGISTER DATA D7 X X X 1 1 0 1 D6 X X X 0 0 0 0 D5 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -- 0 D4 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 D3 X 0 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 D2 X 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -- 0 D1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -- 0 D0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 -- 0
See Table 30 for power-up patterns.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 4. Character and Annunciator Register Address Map in 48/1 Mode
REGISTER Digit 0 5 x 7 matrix character Digit 1 5 x 7 matrix character Digit 2 5 x 7 matrix character UP TO Digit 45 5 x 7 matrix character Digit 46 5 x 7 matrix character Digit 47 5 x 7 matrix character Digit 0 annunciators Digit 1 annunciators Digit 2 annunciators UP TO Digit 45 annunciators Digit 46 annunciators Digit 47 annunciators COMMAND ADDRESS D15 0 0 0 -- 0 0 0 0 0 0 -- 0 0 0 D14 0 0 0 -- 1 1 1 1 1 1 -- 1 1 1 D13 1 1 1 -- 0 0 0 0 0 0 -- 1 1 1 D12 0 0 0 -- 0 0 0 1 1 1 -- 1 1 1 D11 0 0 0 -- 1 1 1 0 0 0 -- 1 1 1 D10 0 0 0 -- 1 1 1 0 0 0 -- 1 1 1 D9 0 0 1 -- 0 1 1 0 0 1 -- 0 1 1 D8 0 1 0 -- 1 0 1 0 1 0 -- 1 0 1 HEX CODE 0x20 0x21 0x22 -- 0x4D 0x4E 0x4F 0x50 0x51 0x52 -- 0x7D 0x7E 0x7F
Table 10 shows how to use the single user-defined font register 0x05 to set the font address pointer, write font data, and read font data. A read action always returns font data from the font address pointer position. A write action sets the 7-bit font address pointer if the MSB is set, or writes 7-bit font data to the font address pointer position if the MSB is clear. The font address pointer autoincrements after a valid access to the user-definable font data. Autoincrementing allows the 120-font data entries to be written and read back very quickly because the font pointer address need only be set once. After the last data location 0xF7 has been written, further font data entries are ignored until the font address pointer is reset. If the font address pointer is set to an out-of-range address by writing data in the 0xF8 to 0xFF range, then address 0x80 is set instead (Table 11). Table 12 shows the user-definable font pointer base addresses. Table 13 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. Table 14 shows the six sequential write commands required to set a MAX6853's font character RAM02 with the data to display character 2 given in Table 9.
register selects one digit's cursor to be lit either continuously or blinking. All the other digits' cursors are off. The 7 least significant bits (LSBs) of the cursor register identify the cursor position. The MSB is clear for the cursor to be on continuously, and set for the cursor to be lit only during the first half of each blink period. The valid cursor position address range is contiguous: 0 to 47 (0x00 to 0x2F) for the first digit row, and 48 to 95 (0x30 to 0x5F) for the last digit row. If the cursor register is programmed with an out-of-range value of 95 to 127 (0x60 to 0x7F), then all cursors are off.
Annunciator Registers
The annunciator registers are organized in bytes, with each segment of each grid being represented by 2 bits. Thus, the four annunciators segments allowed for each grid are represented by exactly 1 byte (Table 16). Annunciators are only available in 48/1 mode. The annunciator address map is shown in Table 4.
Configuration Register
The configuration register is used to enter and exit shutdown, lock the key VFD configuration settings, select the blink rate, globally clear the digit and annunciator data, reset the blink timing, and select between 48/1 and 96/2 display modes (Table 17). Shutdown Mode (S Data Bit D0) Format The S bit in the configuration register selects shutdown or normal operation (Table 18). The display driver can be programmed while in shutdown mode, and shut11
Cursor Register
The cursor register controls the behavior of the cursor segments (Table 15). The MAX6853 controls 48 cursors in 48/1 mode, and 96 cursors in 96/2 mode. The cursor
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 5. Character Register Address Map in 96/2 Mode
REGISTER Digit 0 5 x 7 matrix character, 1st row Digit 1 5 x 7 matrix character, 1st row Digit 2 5 x 7 matrix character, 1st row UP TO Digit 45 5 x 7 matrix character, 1st row Digit 46 5 x 7 matrix character, 1st row Digit 47 5 x 7 matrix character, 1st row Digit 0 5 x 7 matrix character, 2nd row Digit 1 5 x 7 matrix character, 2nd row Digit 2 5 x 7 matrix character, 2nd row UP TO Digit 45 5 x 7 matrix character, 2nd row Digit 46 5 x 7 matrix character, 2nd row Digit 47 5 x 7 matrix character, 2nd row COMMAND ADDRESS D15 0 0 0 -- 0 0 0 0 0 0 -- 0 0 0 D14 0 0 0 -- 1 1 1 1 1 1 -- 1 1 1 D13 1 1 1 -- 0 0 0 0 0 0 -- 1 1 1 D12 0 0 0 -- 0 0 0 1 1 1 -- 1 1 1 D11 0 0 0 -- 1 1 1 0 0 0 -- 1 1 1 D10 0 0 0 -- 1 1 1 0 0 0 -- 1 1 1 D9 0 0 1 -- 0 1 1 0 0 1 -- 0 1 1 D8 0 1 0 -- 1 0 1 0 1 0 -- 1 0 1 HEX CODE 0x20 0x21 0x22 -- 0x4D 0x4E 0x4F 0x50 0x51 0x52 -- 0x7D 0x7E 0x7F
Table 6. Character Registers Format
MODE Writing character data to use font map data with DP segment unlit Writing character data to use font map data with DP segment lit COMMAND ADDRESS 0x20 to 0x4F (48/1 mode) 0x20 to 0x7F (96/2 mode) 0x20 to 0x4F (48/1 mode) 0x20 to 0x7F (96/2 mode) REGISTER DATA D7 0 Bits D6 to D0 select font characters 0 to 127 1 D6 D5 D4 D3 D2 D1 D0
down mode is overridden when in display test mode. For normal operation, set S bit to 1. When the MAX6853 is in shutdown mode, the multiplex oscillator is halted at the end of the current 100s multiplex period (OSC = 4MHz), and the VFBLANK output is used to disable the VFD tube driver. Data in the digit and other control registers remains unaltered. If the PUMP output is configured as a square-wave clock, then the PUMP output is forced low for the duration of shutdown, and the square-wave clock restored when the MAX6853 comes out of shutdown. If the PHASE1 output or PHASE2 output is configured as a filament driver, then that output is forced low for the duration of shutdown and the filament drive waveforms restored when the MAX6853 comes out of shutdown. When the MAX6853 comes out of shutdown, the external VFD tube driver is presumed to contain invalid data. The VFBLANK output is used to disable the VFD tube driver for the first multiplex cycle after exiting shutdown,
12
clearing any invalid data. The next multiplex cycle uses newly sent valid data. Configuration Lock (L Data Bit D1) Format The configuration lock register is a safety feature to reduce the risk of the VFD configuration settings being inadvertently changed due to spurious writes if software fails. When set, the shift-limit register (0x0E), grids register (0x03), and output map data (0x06) can be read but cannot be written. The output map data pointer itself may be written in order to allow the output map data to be read back (Table 19). Blink Rate Selection (B Data Bit D2) Format The B bit in the configuration register selects the blink rate of the cursor and annunciator segments. This is the speed that the segments blink on and off when blinking is selected for these segments. The frequency of the multiplex clock OSC and the setting of the B bit (Table 20) determine the blink rate.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
Global Blink Timing Synchronization (T Data Bit D4) Format Setting the T bit in multiple MAX6853s at the same time (or in quick succession) synchronizes the blink timing across all the devices (Table 21). The display multiplexing sequence is also reset, which can give rise to a one-time display flicker when the register is written. Global Clear Digit Data (R Data Bit D5) Format When the R bit (Table 22) is set, the segment and annunciator data are cleared. Display Mode (M Data Bit D6) Format The M bit (Table 23) selects the display modes (Table 1). The display modes trade the maximum allowable number of digits (mode 96/2) against the availability of annunciator segments (mode 48/1). Blink Phase Readback (P Data Bit D7) Format When the configuration register is read, the P bit reflects the blink phase at that time (Table 24). Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high (Figure 8). Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 9). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX6853, the MAX6853 generates the acknowledge bit because the MAX6853 is the recipient. When the MAX6853 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. In this case, the master acknowledges all bytes received from the MAX6853 except for the last byte required, after which the master issues a STOP condition to signify end of transmission. Slave Address The MAX6853 has a 7-bit-long slave address (Figure 10). The eighth bit following the 7-bit slave address is the R/W bit. Set it low for a write command and high for a read command. The first 5 bits (MSBs) of the MAX6853 slave address are always 11101. Slave address bits A1 and A0 are selected by the address input pins AD0. This input may be connected to GND, V+, SDA, or SCL. The MAX6853 has four possible slave addresses (Table 7) and therefore a maximum of four MAX6853 devices may share the same interface.
MAX6853
Serial Interface
Serial Addressing The MAX6853 operates as a slave that sends and receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX6853, and generates the SCL clock that synchronizes the data transfer (Figure 6). The MAX6853 SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on the SDA. The MAX6853 SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition (Figure 7) sent by a master, followed by the MAX6853 7-bit slave address plus R/W bit (Figure 10), a register address byte, 1 or more data bytes, and finally a STOP condition (Figure 7). Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 7).
Message Format for Writing
A write to the MAX6853 comprises the transmission of the MAX6853's slave address with the R/W bit set to zero, followed by at least 1 byte of information. The first byte of information is the command byte, which determines which register of the MAX6853 is to be written by the next byte, if received. If a STOP condition is detected after the command byte is received, then the MAX6853 takes no further action (Figure 11) beyond storing the command byte. Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX6853 selected by the command byte (Figure 12). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX6853 internal registers because the
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
SDA
tSU, DAT tLOW
SCL
tSU, STA tHD, DAT tHD, STA tSU, STO
tBUF
tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP START CONDITION CONDITION
Figure 6. 2-Wire Serial Interface Timing Details
SDA SDA
SCL S START CONDITION P STOP CONDITION SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
Figure 7. Start and Stop Conditions
START CONDITION SCL 1 2
Figure 8. Bit Transfer
CLOCK PULSE FOR ACKNOWLEDGMENT 7 8 9
SDA BY TRANSMITTER
SDA BY RECEIVER
S
Figure 9. Acknowledge
SDA 1 START MSB 1 1 0 1 A1 A0 LSB R/W ACK
SCL
Figure 10. Slave Address
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX6853 S SLAVE ADDRESS R/W 0 A COMMAND BYTE ACKNOWLEDGE FROM MAX6853 A P D15 D14 D13 D12 D11 D10 D9 D8
Figure 11. Command Byte Received
ACKNOWLEDGE FROM MAX6853 HOW CONTROL BYTE AND DATA BYTE MAP INTO MAX6853's REGISTERS ACKNOWLEDGE FROM MAX6853 S SLAVE ADDRESS R/W 0 A COMMAND BYTE A DATA BYTE 1 BYTE AUTOINCREMENT MEMORY WORD ADDRESS A P D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 ACKNOWLEDGE FROM MAX6853 D5 D4 D3 D2 D1 D0
Figure 12. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX6853 HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX6853'S REGISTERS ACKNOWLEDGE FROM MAX6853 S SLAVE ADDRESS 0 A COMMAND BYTE A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
ACKNOWLEDGE FROM MAX6853 D4 D3 D2 D1 D0
DATA BYTE n BYTES
A
P
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 13. n Data Bytes Received
command byte address generally autoincrements (Table 8) (Figure 13).
Operation with Multiple Masters
If the MAX6853 is operated on a 2-wire interface with multiple masters, a master reading the MAX6853 should use a repeated start between the write, which sets the MAX6853's address pointer, and the read(s) that takes the data from the location(s). This is because it is possible for master 2 to take over the bus after master
Message Format for Reading
The MAX6853 is read using the MAX6853's internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for a write. The pointer generally autoincrements after each data byte is read using the same rules as for a write (Table 8). Thus, a read is initiated by first configuring the MAX6853's command byte by performing a write (Figure 11). The master can now read n consecutive bytes from the MAX6853, with the first data byte being read from the register addressed by the initialized command byte (Figure 13). When performing read-after-write verification, reset the command byte's address because the stored byte address generally is autoincremented after the write (Table 8).
Table 7. MAX6853 Address Map
PIN AD0 GND V+ SDA SCL A6 1 1 1 1 A5 1 1 1 1 DEVICE ADDRESS A4 1 1 1 1 A3 0 0 0 0 A2 1 1 1 1 A1 0 0 1 1 A0 0 1 0 1
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 8. Command Address Autoincrement Rules
COMMAND BYTE ADDRESS RANGE x0000000 to x0000100 x0000110 x0010000 x000111 to x1111110 x1111111 AUTOINCREMENT BEHAVIOR Command byte address autoincrements after byte read or written. Command byte address remains at x0000110 after byte read or written, but the font output map address pointer autoincrements. Factory reserved; do not write to this register. Command byte address autoincrements after byte read or written. Command byte address remains at x1111111 after byte read or written.
1 has set up the MAX6853's address pointer but before master 1 has read the data. If master 2 subsequently changes the MAX6853's address pointer, then master 1's delayed read may be from an unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX6853 to be configured with the shortest number of transmissions by minimizing the number of times the command byte needs to be sent. The command address or the font pointer address stored in the MAX6853 generally increments after each data byte is written or read (Table 8).
condition, VFBLANK is high to disable the VFD tube driver, which is expected to force its driver outputs low to blank the display without altering the contents of its output latches. In the default condition, VFBLANK is low to enable its VFD tube driver outputs to follow the state of the VFD tube driver's output latches. The VFBLANK output is used for PWM intensity control and to disable the VFD tube driver in shutdown.
Multiplex Architecture
The multiplex engine transmits grid and anode control data to the external VFD driver using the VFCLK, VFDOUT, and VFLOAD. The number of data bits m transmitted is set by the user in the shift-limit register (Table 29). Figure 15 is the VFD multiplex timing diagram. The essential rules for multiplex action are as follows: * The external VFD driver's data latch contains the data for the current grid being displayed. * The VFBLANK input is controlled to provide the PWM intensity control. * The VFCLK and VFDOUT outputs are used to fill the external VFD driver's shift register with the multiplex data for the next grid, during the multiplex timeslot for the current grid. * The VFLOAD output loads the new grid-anode data pattern at the start of its multiplex cycle.
VFD Driver Serial Interface
The VFD driver interface on the MAX6853 is a serial interface using three outputs, VFLOAD, VFCLK, and VFDOUT (Figure 14) to drive industry-standard, shiftregister, high-voltage grid/anode VFD tube drivers (Figures 3 and 4). The speed of VFCLK is 2MHz when OSC is 4MHz. The maximum speed of VFCLK is 4MHz when OSC is 8MHz. This interface transfers display data from the MAX6853 to the VFD tube driver. The serial interface bit stream output is programmable up to 122 bits, which are labeled DD0-DD121. The functions of the three interface outputs are as follows: VFCLK is the serial clock output, which shifts data on its falling edge from the MAX6853's 122-bit output shift register to VFLOAD. VFDOUT is the serial data output. The data changes on VFCLK's falling edge, and is stable when it is sampled by the display driver on the rising edge of VFCLK. VFLOAD is the latch-load output. VFLOAD is high to transfer data from the display tube driver's shift register to the display driver's output latch (transparent mode), and low to retain that data in the display driver's output latch. A fourth output, VFBLANK, provides gating control of the tube driver. VFBLANK can be configured to be either high or low using the VBLANK polarity register (Table 27) to enable the VFD tube driver. In the default
Grids Register
The grids register sets how many grids are multiplexed from 1 to 48 (Table 25). When the grids register is written, the external VFD tube driver is presumed to contain invalid data. The VFBLANK output disables the VFD tube driver for the first multiplex cycle after exiting shutdown, clearing any invalid data. The next multiplex cycle uses newly sent valid data. If the grids register is written with an out-ofrange value of 0x30 to 0xFF, then the value 0x2F is stored instead.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
Intensity Register
Digital control of display brightness is provided by pulse-width modulation of the tube blanking time, which is controlled by the lower nibble of the intensity register (Table 26). The modulator scales the VFBLANK output in 15 steps from a minimum of 1/16 up to 15/16 of each grid's multiplex period (Figure 16). Figure 17 shows the modulator behavior when the VFBLANK polarity register is set to 0x00 (Table 27), so VFBLANK is high to disable (blank) the display. The minimum off-time period of a 1/16 multiplex period (6.25s with OSC = 4MHz) is always at the start of the multiplex cycle. This allows time for slow display drivers to turn off, and slow display phosphors time to decay between grids. Thus, image ghosting is avoided. If a display has very slow phosphor, double the allowed decay time by not using a 15/16 duty cycle.
MAX6853
Table 9. Character Map
MSB x000 LSB RAM16 x001 x010 x011 x100 x101 x110 x111
0000
RAM00
0001
RAM01
RAM17
0010
RAM02
RAM18
0011
RAM03
RAM19
VFBLANK Polarity Register
The VFBLANK polarity register sets the active level of the VFBLANK output pin (Table 27).
0100
RAM04
RAM20
0101
RAM05
RAM21
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches the drivers between one of two modes: normal and display test. Display-test mode turns all segments and annunciators on and sets the duty cycle to 7/16 (halfpower) (Table 28). Reading the display-test and device ID register returns the MAX6853 device ID 0b0000 011 that identifies the driver type, plus the display-test status in the LSB.
0110
RAM06
RAM22
0111
RAM07
RAM23
1000
RAM08
1001
RAM09
Output Shift-Limit Register
The output serial interface transfers display data from the MAX6853 to the display driver. The serial interface bit-stream output length is programmable up to 122 bits, which are labeled DD0-DD121. Set the number of bits with the shift-limit register, address 0x0E. If the shift-limit register is written with an out-of-range value 0x7A to 0xFF, then the value 0x79 is stored instead. Table 29 shows the shift-limit register.
1010 RAM10
1011
RAM11
1100
RAM12
Output Map
The output map comprises 122 words of 7-bit RAM. The output map data should be written when the MAX6853 is configured after power-up. Table 30 shows the output map RAM codes.
1101 RAM13
1110
RAM14
1111
RAM15
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
VFLOAD tVCL VFCLK tVDS tVCH tVCP tVCSH tVCSW
VFDOUT
DD0
DD1
M-1
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
Figure 14. VFD Interface Timing Diagram
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100s TIMESLOT GRID 0 100s TIMESLOT GRID 1 100s TIMESLOT GRID N-4 100s TIMESLOT GRID N-3 100s TIMESLOT GRID N-2 100s TIMESLOT GRID N-1
START OF NEXT CYCLE
100s TIMESLOT GRID 0
500ns 500ns 500ns 500ns
GRID 0's 100s MULTIPLEX TIMESLOT
VFCLK
VFDOUT
DD0
DD1 DD2
DD3
DD4 DD5 DD6 DD7
DD8 DD9 DD10
M-4
M-3
M-2 M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT VFLOAD
Figure 15. VFD Multiplex Timing Diagram
The output map is an indirect addressing reference table. It translates bit position in the output shift register (valid range: from zero to the value in shift-limit register 0x0E) to bit function. Any output shift-register bit position may be set to any grid, 5 x 7 matrix segment, DP segment, annunciator segment, or cursor segment. The power-up default pattern for output map RAM maps a 40-digit, two-digits-per-grid display with DPs and cursors (Table 31). Selecting an unused map RAM entry (126 or 127) for an output shift-register position always resets the corresponding output bit to low (segment or grid OFF). When selecting an invalid map RAM entry (for example, codes 48 to 83 to select annunciators in 96/2 mode, which does not support annunciators), the corresponding output bit is always low (segment or grid OFF).
If the map RAM entry corresponds to a nonexistent font segment (no action in Table 30) when the digit data is processed through the character font, then the result again is zero (segment or grid OFF). The output map data is indirectly accessed by an autoincrementing output map address pointer in the MAX6853 at address 0x06. The output map address pointer can be written (i.e., set to an address between 0x00 and 0x79) but cannot be read back. The output map data is written and read back through the output map address pointer. Table 32 shows how to set the output map address pointer to a value within the acceptable range. Bit D7 is set to denote that the user is writing the output map address pointer. If the user attempts to set the output map address to one of the out-of-range addresses by writing data in range 0xFA to 0xFF, then address 0x00 is set instead.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100s TIMESLOT GRID 0 100s TIMESLOT GRID 1 100s TIMESLOT GRID N-4 100s TIMESLOT GRID N-3 100s TIMESLOT GRID N-2 100s TIMESLOT GRID N-1
START OF NEXT CYCLE
100s TIMESLOT GRID 0
MINIMUM 6.25s INTERDIGIT BLANKING INTERVAL (OSC = 4MHz) VFBLANK GRID 0'S 100s MULTIPLEX TIMESLOT
1/16TH (MIN ON)
2/16TH
3/16TH
4/16TH
5/16TH
6/16TH
7/16TH
8/16TH
9/16TH
10/16TH
11/16TH
12/16TH
13/16TH
14/16TH
15/16TH 15/16TH (MAX ON)
Figure 16. BLANK and Intensity Timing Diagram
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
100s MULTIPLEX TIME PERIOD (OSC = 4MHz) 1-1 SEG 1 1-2 SEG 6 1-3 SEG 11 1-4 SEG 16 1-5 SEG 21 1-6 SEG 26 1-7 SEG 31 2-1 SEG 2 2-2 SEG 7 2-3 SEG 12 2-4 SEG 17 2-5 SEG 22 2-6 SEG 27 2-7 SEG 32 3-1 SEG 3 3-2 SEG 8 3-3 SEG 13 3-4 SEG 18 3-5 SEG 23 3-6 SEG 28 3-7 SEG 33 CURSOR 4-1 SEG 4 4-2 SEG 9 4-3 SEG 14 4-4 SEG 19 4-5 SEG 24 4-6 SEG 29 4-7 SEG 34 5-1 SEG 5 5-2 SEG 10 5-3 SEG 15 5-4 SEG 20 5-5 SEG 25 PHASE 1 (A) (B) (C) (E) (D)
PHASE 2
Figure 18. Filament Bridge Driver Timing Waveforms
VFIL R2 Q2 Q4 R4
5-6 SEG 30 5-7 SEG 35
VFD TUBE
PHASE 1 PHASE 2 Q1 Q3 GND GND
Figure 17. Relationship Between Segment Output and VFD Tube 5 7 Matrix Dots
Figure 19. Filament Bridge Driver (MOSFET)
After the last data location 0xF9 has been written, further output map data entries are ignored until the output map address pointer is reset. The output map data can be written to the address set by the output map address pointer. Bit D7 is clear to denote that the user is writing actual output map data. The output map address pointer is autoincremented after the output map data has been written to the current location. If the user writes the output map data in the RAM order, then the output map address pointer need only be set once, or even not at all as the address is set to 0x00 as power-up default (Table 33). The output map data can be read by reading address 0x86. The 7-bit output map data at the address set by the output map address pointer is read back, with the MSB clear. The output map address pointer is autoincremented after the output map data has been read from the current location, in the same way as for a write (Table 34).
the filament must be powered by a DC-to-AC or DC-toDC converter. The MAX6853 can generate the waveforms on the PHASE1 and PHASE2 outputs to drive the VFD filament using a full bridge (push-pull drive). The PHASE1 and PHASE2 outputs can be used as general-purpose outputs if the filament drive is not required. The bridge drive transistors are external, but the waveforms are generated by the MAX6853. The waveform generation uses PWM to set the effective RMS voltage across the filament, as a fraction of the external supply voltage (Figure 18) (Table 35). The filament switching frequency is synchronized to the multiplex scan clock, eliminating beating artifacts due to differing filament and multiplex frequencies. The PWM duty cycle is controlled by the filament dutycycle register (Table 36). The effective RMS voltage across the filament is given by the expression: VRMS = FilOn x (VFIL - VLO-BRIDGE - VHI-BRIDGE) / 200 or, rearranged: Duty = 200 x VRMS / (VFIL - VLO-BRIDGE - VHI-BRIDGE) where:
Filament Drive
The VFD filament is typically driven with an AC waveform, supplied by a center-tapped 50Hz or 60Hz power transformer as part of the system power supply. However, if the system has only DC supplies available,
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
FilOn is the number to store in the filament duty-cycle register, address 0x09. VFIL is the supply voltage to the filament driver bridge (V). VRMS is the specified nominal filament supply voltage (V). V LO-BRIDGE is the voltage drop across a low-side bridge driver (V). V HI-BRIDGE is the voltage drop across a high-side bridge driver (V). The minimum commutation time, shown at (C) in Figure 18, is set by (2/OSC)s (500ns when OSC = 4MHz) to ensure that shoot-through currents cannot flow during phase reversal. Otherwise, the duty cycle of the bridge sets the RMS voltage across the filament. This technique provides a low-cost AC filament supply when using a regulated supply higher than the RMS voltage rating of the filament. Figure 19 shows the external components required for the filament driver using a FET bridge.
PUMP Output
Program the PUMP output as one of four output types (Table 41).
MAX6853
Multiplex Clock and Blink Timing
The OSC1 and OSC2 inputs set the multiplex and blink timing for the display driver. Connect an external resistor from OSC2 to GND and an external capacitor COSC from OSC1 to GND to set the frequency of the internal RC oscillator. Alternatively, overdrive OSC1 with an external TTL or CMOS clock. Use an external clock ranging between 2MHz and 8MHz to drive OSC1 to produce an exact blink rate or multiplier period. The multiplex clock frequency determines the multiplex scan rate and the blink timing. The display scan rate is {OSC / 400 / (1 + grids register value)}. There are 400 OSC cycles per digit multiplex period. For example, with OSC = 4MHz, each display digit is enabled for 100s. For a 40-grid display tube (grids register value = 39 or 0x27), the display scan rate is 250Hz. The BLINK output is the selectable blink period clock. It is nominally 0.5Hz or 1Hz (OSC = 4MHz). It is low during the first half of the blink period, and high during the second half. The PORT0 and PORT1 general-purpose outputs may be programmed to be BLINK output. Synchronize the BLINK timing if desired by setting the T bit in the configuration register (Table 21). The RC oscillator uses an external resistor ROSC and an external capacitor COSC to set the oscillator frequency. ROSC connects from OSC2 to ground. COSC connects from OSC1 to ground. The following values of R OSC and C OSC set the oscillator to 4MHz, which makes the BLINK frequencies 0.5Hz and 1 Hz: fOSC = KF / (ROSC x [COSC + CSTRAY]) MHz where: KF = 2320 ROSC = external resistor in k (allowable range 8k to 80k) COSC = external capacitor in pF CSTRAY = stray capacitance from OSC1 to GND in pF, typically 2pF For OSC = 4MHz, ROSC is 10k and COSC is 56pF. The effective value of COSC includes not only the actual external capacitor used, but also the stray capacitance from OSC1 to GND. This capacitance is usually in the 1pF to 5pF range, depending on the layout used. The allowed range of fOSC is 2MHz to 8MHz. If fOSC is set too high, the internal oscillator can stop working. An internal fail-safe circuit monitors the multiplex clock and
21
PHASE1 and PHASE2 Outputs
PHASE1 and PHASE2 can be individually programmed as one of four output types (Tables 37, 38). When using the filament drive, first ensure that the filament duty-cycle register 0x09 is set to the correct value before configuring the PHASE1 and PHASE2 outputs to be filament drives. To stop the filament drive, program either PHASE1 or PHASE2 (or both) to be logic-low general-purpose outputs. Both PHASE1 and PHASE2 outputs come out of power-on-reset in logic-low condition.
PORT0 and PORT1 Outputs
PORT0 and PORT1 can be individually programmed as one of eight output types (Tables 39, 40). The PORT1 choices are similar to the PORT0 choices, except that the last four items are invert logic. PORT0 output comes out of power-on-reset in logic-low condition, whereas PORT1 output initializes high. The PORT0 and PORT1 shutdown outputs allow external hardware (for example, a DC-to-DC converter power supply for VFD) to be disabled by the MAX6853 when the MAX6853 is shut down. The 625Hz, 1250Hz, and 2500Hz outputs can drive a piezo sounder either from PORT0 or PORT1 alone, or by both ports together as bridge drive. For bridge drive, the sounder is connected between PORT0 and PORT1, taking advantage of the PORT1 output being inverted with respect to PORT0. Select different frequencies for PORT0 and PORT1 to obtain a wider range of sounds when bridge drive is used.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
detects a slow or nonworking multiplex clock. When a slow or nonworking multiplex clock is detected, an internal fail-safe oscillator generates a replacement clock of about 200kHz. This backup clock ensures that the VFD is not damaged by the multiplex operation halting inadvertently. The scan rate for 16 digits is about 15Hz in fail-safe mode, and the display flickers. A flickering display is a good indication that there is a problem with the multiplex clock.
Power Supplies
The MAX6853 operates from a single 2.7V to 3.6V power supply. Bypass the power supply to GND with a 0.1F capacitor as close to the device as possible. Add a bulk capacitor (such as a low-cost electrolytic 1F to 22F) if the MAX6853 is driving high current from any of the general-purpose output ports.
Table 10. Memory Mapping of User-Defined Font Register 0x05
COMMAND ADDRESS 0x05 0x05 0x05 REGISTER DATA 0x00-0x7F 0x00-0x7F 0x80-0xFF READ OR WRITE Read Write Write FUNCTION Read 7-bit user-definable font data entry from current font address. MSB of the register data is clear. Font address pointer is incremented after the read. Write 7-bit user-definable font data entry to current font address. Font address pointer is incremented after the write. Write font address pointer with the register data.
Table 11. Font Pointer Address Behavior
FONT POINTER ADDRESS 0x80 to 0xF6 0xF7 0xF8 to 0xFF ACTION Valid range to set the font address pointer. Pointer autoincrements after a font data read or write, while pointer address remains in this range. Further font data is ignored after a font data read or write to this pointer address. Invalid range to set the font address pointer. Pointer is set to 0x80.
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 12. User-Definable Font Pointer Base Address Table
FONT CHARACTER RAM00 RAM01 RAM02 RAM03 RAM04 RAM05 RAM06 RAM07 RAM08 RAM09 RAM10 RAM11 RAM12 RAM13 RAM14 RAM15 RAM16 RAM17 RAM18 RAM19 RAM20 RAM21 RAM22 RAM23 COMMAND ADDRESS 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 REGISTER DATA 0x80 0x85 0x8A 0x8F 0x94 0x99 0x9E 0xA3 0xA8 0xAD 0xB2 0xB7 0xBC 0xC1 0xC6 0xCB 0xD0 0xD5 0xDA 0xDF 0xE4 0xE9 0xEE 0xF3 REGISTER DATA D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 D4 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 D3 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 D2 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 13. User-Definable Character Storage Example
FONT CHARACTER RAM00 RAM00 RAM00 RAM00 RAM00 RAM01 RAM01 RAM01 RAM01 RAM01 RAM02 RAM02 RAM02 RAM02 RAM02 FONT ADDRESS POINTER 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E COMMAND ADDRESS 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 REGISTER DATA D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 D5 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 D4 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 D3 1 0 1 0 1 0 0 1 0 0 0 0 0 1 0 D2 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 D1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 D0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 0
Table 14. Setting a Font Character to RAM Example
COMMAND ADDRESS 0x05 0x05 0x05 0x05 0x05 0x05 REGISTER DATA 0x8A 0x42 0x61 0x51 0x49 0x46 ACTION BEING PERFORMED Set font address pointer to the base address of font character RAM02. 1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements to address 0x8B. 2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then autoincrements to address 0x8C. 3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then autoincrements to address 0x8D. 4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then autoincrements to address 0x8E. 5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements to address 0x8F.
Table 15. Cursor Register Format
MODE Cursor register. Digit 1's cursor is lit continuously. Digit 1's cursor is lit only for the first half of each blink period. UP TO Digit 96's cursor is lit continuously. Digit 96's cursor is lit only for the first half of each blink period. No cursor is lit. COMMAND ADDRESS 0x0F 0x0F 0x0F 0x0F 0x0F 0x0F 0x0F 0 1 X 1 1 1 0 0 1 REGISTER DATA D7 BLINK 0 1 0 0 0 0 D6 D5 D4 0 0 UP TO 1 1 X 1 1 X 1 1 X 1 1 X 1 1 X D3 0 0 D2 0 0 D1 0 0 D0 0 0 CURSOR POSITION
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 16. Annunciator Registers Format
ANNUNCIATOR BYTE BIT ALLOCATIONS Annunciator A1 is off. Annunciator A1 is lit only for the first half of each blink period. Annunciator A1 is lit only for the second half of each blink period. Annunciator A1 is lit continuously. Annunciator A2 is off. Annunciator A2 is lit only for the first half of each blink period. Annunciator A2 is lit only for the second half of each blink period. Annunciator A2 is lit continuously. Annunciator A3 is off. Annunciator A3 is lit only for the first half of each blink period. Annunciator A3 is lit only for the second half of each blink period. Annunciator A3 is lit continuously. Annunciator A4 is off. Annunciator A4 is lit only for the first half of each blink period. Annunciator A4 is lit only for the second half of each blink period. Annunciator A4 is lit continuously. REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR A4 A3 A2 A1 X X X X X X X X X X X X 0 0 1 1 X X X X X X X X X X X X 0 1 0 1 X X X X X X X X 0 0 1 1 X X X X X X X X X X X X 0 1 0 1 X X X X X X X X 0 0 1 1 X X X X X X X X X X X X 0 1 0 1 X X X X X X X X 0 0 1 1 X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X
Table 17. Configuration Register Format
MODE Configuration register REGISTER DATA D7 P D6 M D5 R D4 T D3 X D2 B D1 L D0
Table 19. Configuration Lock (L Data Bit D1) Format
MODE REGISTER DATA D7 P P D6 M M D5 R R D4 T T D3 X X D2 B B D1 0 1 D0 S S
S Unlocked Locked
Table 18. Shutdown Control (S Data Bit D0) Format
MODE Shutdown Normal operation REGISTER DATA D7 P P D6 M M D5 R R D4 T T D3 X X D2 B B D1 L L D0 0 1
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 20. Blink Rate Selection (B Data Bit D2) Format
MODE Slow blinking (cursor and annunciators blink on for 1s, off for 1s, for OSC = 4MHz) Fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for OSC = 4MHz) REGISTER DATA D7 P P D6 M M D5 R R D4 T T D3 X X D2 0 1 D1 L L D0 S S
Table 21. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE Blink timing counters are unaffected. Blink timing counters are cleared during the I2C acknowledge. REGISTER DATA D7 P P D6 M M D5 R R D4 0 1 D3 X X D2 B B D1 L L D0 S S
Table 22. Global Clear Digit Data (R Data Bit D5) Format
MODE Segment and annunciator data are unaffected. Segment and annunciator data (address range 0x20 to 0x7F) are cleared during the I2C acknowledge. REGISTER DATA D7 P P D6 M M D5 0 1 D4 T T D3 X X D2 B B D1 L L D0 S S
Table 23. Display Mode (M Data Bit D6) Format
MODE 48/1 96/2 DISPLAY TYPE Up to 48 digits, 1 digit per grid Up to 96 digits, 2 digits per grid REGISTER DATA D7 P P D6 0 1 D5 R R D4 T T D3 X X D2 B B D1 L L D0 S S
Table 24. Blink Phase Readback (P Data Bit D7) Format
MODE P1 blink phase P0 blink phase REGISTER DATA D7 0 1 D6 M M D5 R R D4 T T D3 X X D2 B B D1 L L D0 S S
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 25. Grids Register Format
GRIDS Display has 1 grid: G0 Display has 2 grids: G0 and G1 Display has 3 grids: G0 to G2 Display has 4 grids: G0 to G3 UP TO Display has 45 grids: G0 to G44 Display has 46 grids: G0 to G45 Display has 47 grids: G0 to G46 Display has 48 grids: G0 to G47 COMMAND ADDRESS 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 REGISTER DATA D7 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 -- 1 1 1 1 D4 0 0 0 0 -- 0 0 0 0 D3 0 0 0 0 -- 1 1 1 1 D2 0 0 0 0 -- 1 1 1 1 D1 0 0 1 1 -- 0 0 1 1 D0 0 1 0 1 -- 0 1 0 1 HEX CODE 0x00 0x01 0x02 0x03 -- 0x2C 0x2D 0x2E 0x2F
Table 26. Intensity Register Format
DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) VFBLANK BEHAVIOR (OSC = 4MHz) High for 6.25s, low for 6.25s, high for 87.5s High for 6.25s, low for 12.5s, high for 81.25s High for 6.25s, low for 18.75s, high for 75s High for 6.25s, low for 25s, high for 68.75s High for 6.25s, low for 31.25s, high for 62.5s High for 6.25s, low for 37.5s, high for 56.25s High for 6.25s, low for 43.75s, high for 50s High for 6.25s, low for 50s, high for 43.75s High for 6.25s, low for 56.25s, high for 37.5s High for 6.25s, low for 62.5s, high for 31.25s High for 6.25s, low for 68.75s, high for 25s High for 6.25s, low for 75s, high for 18.75s High for 6.25s, low for 81.25s, high for 12.5s High for 6.25s, low for 87.5s, high for 6.25s High for 6.25s, low for 93.75s High for 6.25s, low for 93.75s COMMAND ADDRESS 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 REGISTER DATA D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7 0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 27. VFBLANK Polarity Register Format
GRIDS VFBLANK is high to disable the display. VFBLANK is low to disable the display. COMMAND ADDRESS 0x01 0x01 REGISTER DATA D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 0 1 D0 0 0 HEX CODE 0xX0 0xX2
Table 28. Display-Test and Device ID Register Format
MODE Normal operation Display test Read MAX6853 device ID and display test status COMMAND ADDRESS 0x07 0x07 0x07 REGISTER DATA D7 X X 0 D6 X X 0 D5 X X 0 D4 X X 0 D3 X X 0 D2 X X 1 D1 X X 1 D0 0 1 DT
Table 29. Shift-Limit Register Format
SHIFT LIMIT Minimum setting example (01) Maximum setting example (121 or 0x79) COMMAND ADDRESS 0x0E 0x0E REGISTER DATA D7 0 0 D6 0 1 D5 0 1 D4 0 1 D3 0 1 D2 0 0 D1 0 0 D0 1 1 HEX CODE 0x01 0x79
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 30. Output Map RAM Codes
OUTPUT MAP RAM CODE (DECIMAL) 0 to 47 48, 49, 50, 51, 52 53, 54, 55, 56, 57 58, 59, 60, 61, 62 63, 64, 65, 66, 67 68, 69, 70, 71, 72 73, 74, 75, 76, 77 78, 79, 80, 81, 82 83 5 x 7 matrix character segments Digits 48 to 95 only 84, 85, 86, 87, 88 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 Use character registers 0x50 to 0x7F (Figure 12) Only valid for 96/2 mode (display mode select bit M = 1) -- 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 -- 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 -- 4 annunciators 120 to 123 Only valid for 48/1 mode (display mode select bit M = 0) Cursor Cursor 125 Only valid for 96/2 mode (display mode select bit M = 1) Unused Cursor segment for digits 48 to 95 only Annunciator A1 to annunciator A4 5 x 7 matrix character segment DP Digits 0 to 47 only Use character registers 0x20 to 0x4F (Figure 12) 5 x 7 matrix character segments APPLICATION 48 grids FUNCTION MAPPED BY OUTPUT MAP RAM CODE Grids G0 to G47 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 5 x 7 matrix character segment DP
89, 90, 91, 92, 93 94, 95, 96, 97, 98 99, 100, 101,102, 103 104, 105, 106, 107, 108 109, 110, 111, 112, 113 114, 115, 116, 117, 118 119
124
Cursor segment for digits 0 to 47 only
126, 127
No action
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 31. Output Map RAM Initial Power-Up Status
OUTPUT MAP RAM ADDRESS 0x00 to 0x27 0x28, 0x29, 0x2A, 0x2B, 0x2C 0x2D, 0x2E, 0x2F, 0x30, 0x31 0x32, 0x33, 0x34, 0x35, 0x36 0x37, 0x38, 0x39, 0x3A, 0x3B 0x3C, 0x3D, 0x3E, 0x3F, 0x40 0x41, 0x42, 0x43, 0x44, 0x45 0x46, 0x47, 0x48, 0x49, 0x4A 0x4B 0x4C, 0x4D, 0x4E, 0x4F, 0x50 0x51, 0x52, 0x53, 0x54, 0x55 0x56, 0x57, 0x58, 0x59, 0x5A 0x5B, 0x5C, 0x5D, 0x5E, 0x5F 0x60, 0x61, 0x62, 0x63, 0x64 0x65, 0x66, 0x67, 0x68, 0x69 0x6A, 0x6B, 0x6C, 0x6D, 0x6E 0x6F 0x70 0x71 0x72 to 0x79 OUTPUT MAP RAM CODE ON POWER-UP (DECIMAL) 0-39 48, 49, 50, 51, 52 53, 54, 55, 56, 57 58, 59, 60, 61, 62 63, 64, 65, 66, 67 68, 69, 70, 71, 72 73, 74, 75, 76, 77 78, 79, 80, 81, 82 83 84, 85, 86, 87, 88 89, 90, 91, 92, 93 94, 95, 96, 97, 98 99, 100, 101,102, 103 104, 105, 106, 107, 108 109, 110, 111, 112, 113 114, 115, 116, 117, 118 119 124 125 127 FUNCTION MAPPED BY OUTPUT MAP RAM CODE Grids 0-39 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 5 x 7 matrix character segment DP 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 5 x 7 matrix character segment DP Cursor segment for digits 0 to 47, 1st row Cursor segment for digits 0 to 47, 2nd row No action
Table 32. Setting Output Map Address Pointer
MODE Set output map address to minimum (0x00) with data 0x80. (Note that this address is set as a power-up default.) Set output map address to maximum 0x79 with data 0xF9. COMMAND ADDRESS 0x06 REGISTER DATA D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
0x06
1
1
1
1
1
0
0
1
Table 33. Writing Output Map Data
MODE Write output map data; output map address pointer is autoincremented after the output map data has been written to the current location. COMMAND ADDRESS 0x06 REGISTER DATA D7 0 D6 D5 D4 D3 D2 D1 D0
7 bits of output map data
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 34. Reading Output Map Data
MODE Read output map data; output map address pointer is autoincremented after the output map data has been read from the current location. COMMAND ADDRESS 0x06 REGISTER DATA D7 0 D6 D5 D4 D3 D2 D1 D0
7 bits of output map data
Table 35. Filament Bridge Driver Timing
TIMING POINT (A) (B) (C) (D) (E) Total 4MHz cycles (OSC = 4MHz) PHASE1 BEHAVIOR Low for (199 - FilOn) cycles Low for (FilOn) cycles Low for (2) cycles High for (FilOn) cycles Low for (199 - FilOn) cycles 400 cycles = 100s PHASE2 BEHAVIOR Low for (199 - FilOn) cycles High for (FilOn) cycles Low for (2) cycles Low for (FilOn) cycles Low for (199 - FilOn) cycles 400 cycles = 100s EXAMPLE 1 DUTY = 1 (MIN) 198 1 2 1 198 400 cycles = 100s EXAMPLE 2 DUTY = 100 99 100 2 100 99 400 cycles = 100s EXAMPLE 3 DUTY = 198 1 198 2 198 1 400 cycles = 100s
Table 36. Filament Duty-Cycle Register Format
FILAMENT DUTY CYCLE Minimum setting example (01) Maximum setting example (199 or 0xC7) COMMAND ADDRESS 0x09 0x09 REGISTER DATA D7 0 1 D6 0 1 D5 0 0 D4 0 0 D3 0 0 D2 0 1 D1 0 1 D0 1 1 HEX CODE 0x01 0xC7
Table 37. PHASE1 Register Format
PHASE1 BEHAVIOR General-purpose output, logic 0. This is the power-up condition. General-purpose output, logic 1. Output gives blink status: zero if blink phase P0; 1 if blink phase P1. Filament drive PHASE1 (logic 0 during shutdown). COMMAND ADDRESS 0x0A 0x0A 0x0A 0x0A REGISTER DATA D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 D0 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 38. PHASE2 Register Format
PHASE2 BEHAVIOR General-purpose output, logic 0. This is the power-up condition. General-purpose output, logic 1. Output gives blink status: zero if blink phase P0; 1 if blink phase P1. Filament drive PHASE2 (logic 0 during shutdown). COMMAND ADDRESS 0x0B 0x0B 0x0B 0x0B REGISTER DATA D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 D0 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3
Table 39. PORT0 Register Format
PORT0 PORT BEHAVIOR General-purpose output, logic 0. This is the power-up condition. General-purpose output, logic 1. Output gives blink status: zero if blink phase P0; 1 if blink phase P1. Output blink status: 1 if blink phase P0; zero if blink phase P1. 625Hz square-wave output zero in shutdown. 1250Hz square-wave output zero in shutdown. 2500Hz square-wave output zero in shutdown. Output gives shutdown status: zero if shutdown mode; 1 if operating mode. COMMAND ADDRESS 0x0C 0x0C 0x0C 0x0C 0x0C 0x0C 0x0C 0x0C REGISTER DATA D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 X X X X X X X X D3 X X X X X X X X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Table 40. PORT1 Register Format
PORT1 PORT BEHAVIOR General-purpose output, logic 0. General-purpose output, logic 1. This is the power-up condition. Output gives blink status: zero if blink phase P0; 1 if blink phase P1. Output blink status: 1 if blink phase P0; zero if blink phase P1. Inverted 625Hz square-wave output 1 in shutdown. Inverted 1250Hz square-wave output 1 in shutdown. Inverted 2500Hz square-wave output 1 in shutdown. Output gives inverted shutdown status: 1 if shutdown mode; zero if operating mode. COMMAND ADDRESS 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D REGISTER DATA D7 X X X X X X X D6 X X X X X X X D5 X X X X X X X D4 X X X X X X X D3 X X X X X X X D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6
0x0D
X
X
X
X
X
1
1
1
0xX7
Table 41. PUMP Register Format
PUMP PORT BEHAVIOR General-purpose output, logic 0. This is the power-up condition. General-purpose output, logic 1. 80kHz square-wave output (OSC = 4MHz) (logic 0 during shutdown). 80kHz square-wave output (OSC = 4MHz) (logic 1 during shutdown). COMMAND ADDRESS 0x08 0x08 0x08 0x08 REGISTER DATA D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 D0 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller MAX6853
Functional Diagram
PWM BRIGHTNESS CONTROL OUTPUT SHIFTER OUTPUT MAP RAM FILAMENT PWM PHASE 1 PHASE 2 PUMP PORT 0 PORT 1
Pin Configuration
TOP VIEW
OSC1 OSC2
CLOCK GENERATOR
VFBLANK VFCLK 1 VFDOUT VFCLK VFLOAD VFDOUT 2 VFLOAD 3 VFBLANK 4 PUMP 5 PHASE1 6 16 OSC1 15 OSC2 14 PORT1
MAX6853
13 AD0 12 SDA 11 SCL 10 PORT0 9 GND
CHARACTERGENERATOR ROM
USER OUTPUTS
PHASE2 7 V+ 8
QSOP
RAM
CONFIGURATION REGISTERS
SCL SDA AD0
2-WIRE SERIAL INTERFACE
Chip Information
TRANSISTOR COUNT: 199,083 PROCESS: CMOS
MAX6853
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2-Wire Interfaced, 5 7 Matrix VacuumFluorescent Display Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX6853
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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